The present invention relates to a non-volatile memory cell read amplifier, applicable, in particular, to EPROM, EEPROM, and FLASH EEPROM memories. The present invention relates more particularly to a read amplifier with a differential output stage.
To read data present in a non-volatile memory cell, the programmed or erased state of which determines the value of the data saved in the memory cell, it is common to use a read amplifier to detect the programmed or erased state of the cell by comparing a current passing through the cell with a reference current. The programed state corresponds conventionally to the storage of a 0 and the erased state to the storage of a 1, or vice-versa. Some known read amplifiers comprise an output stage formed by an inverting gate, while others comprise a differential output stage.
A prior art read amplifier with a differential output stage is represented in FIG. 1. In this figure and in the rest of the present application, PMOS type transistors are designated by references starting by xe2x80x9cTPxe2x80x9d and NMOS type transistors are designated by references starting by xe2x80x9cTNxe2x80x9d.
The read amplifier SA1 comprises a reference stage RFST, a read stage RDST and a differential stage DIFST1 electrically supplied by a voltage Vcc and receiving a reference voltage Vref delivered by a generator RGEN. The read amplifier SA1 has an output node SENSEOUT to be linked to a memory cell to be read, and an output node DATAOUT delivering data at 1 (Vcc) or at 0 (ground) depending on the conductivity state of the memory cell.
The generator RGEN comprises for example a transistor TP0, the source S of which receives the voltage Vcc, the drain D of which is connected to a current generator IGEN, and the gate G of which is linked to the drain D. The transistor TP0 is passed through by a current Iref imposed by the current generator IGEN, and the voltage Vref is sampled at its gate G.
The reference stage RFST comprises two transistors TP1, TN1 in series. The transistor TP1 receives the voltage Vcc at its source, the signal Vref at its gate, and its drain is connected to the drain of the transistor TN1, the source of which is linked to ground.
The read stage RDST comprises two transistors TP2, TN2 in series. The transistor TP2 receives the voltage Vcc at its source, the voltage Vref at its gate, and its drain is connected to the drain of the transistor TN2. The source of the transistor TN2 is connected to the gate of the transistor TN1 and forms the output SENSEOUT of the read amplifier, at which a voltage VSENSE is found.
The differential output stage DIFST1 comprises a first branch comprising two transistors TP3, TN3 in series and a second branch comprising two transistors TP4, TN4 in series. The transistor TP3 receives the voltage Vcc at its source, a voltage VMAT sampled from the drain of the transistor TP2 (also the drain of the transistor TN2) at its gate, and its drain is connected to the drain of the transistor TN3, the source of which is linked to ground. The transistor TP4 receives the voltage Vcc at its source, the voltage Vref at its gate, and its drain is connected to the drain of the transistor TN4, the source of which is linked to ground. The transistor TN4 has its drain connected to its gate, and its gate is connected to the gate of the transistor TN3. The output DATAOUT is formed by the mid-point of the transistors TP3, TN3, i.e., the drain of the transistor TP3 and the drain of the transistor TN3.
The read amplifier also comprises a precharge transistor TP5, the source of which receives the voltage Vcc, and the drain of which is linked to the drain of the transistor TN2. The gate of the transistor TP5 is driven by a voltage Vp. The transistors TP0, TP1, TP2, TP3, TP4 are preferably identical and the transistors TN1, TN2, TN3, TN4 are also identical (same gate aspect ratio).
As an example of an application, it will now be assumed that the output SENSEOUT is linked to a memory cell MCELL through a column decoder COLDEC and a bit line BLj of a memory array MA. The memory cell comprises a floating-gate transistor FGT receiving a read voltage Vread at its gate and the conductivity state of which depends on its programmed or erased state.
The reading of the memory cell MCELL is preceded by a precharge phase during which the voltage Vp is taken to 0. The transistor TP5 is in a transmission state and a precharge current is delivered by the output SENSEOUT. This precharge current charges stray capacitances of the bit line BLj and brings the voltage VSENSE to a determined value, in the order of Vtn (threshold voltage of an NMOS transistor). The transistor TP5 allows the precharge time to be accelerated and, as a result, the global read time, as the transistor TP2 operates as a current generator and is not capable of delivering a high precharge current. During the precharge phase, the voltage VMAT is equal to Vcc and the transistor TP3 is blocked. The transistor TN4 is passed through by the current Iref present in the generator RGEN based upon a current mirror effect between the transistors TP4 and TP0. The transistor TN3 is also passed through by the current Iref based upon a current mirror effect with the transistor TN3. The output DATAOUT is therefore at 0.
The read step starts when the voltage Vp is taken to Vcc. The transistor TP5 is then blocked. The output SENSEOUT delivers in the bit line BLj a current Icell, the value of which depends on the conductivity state of the memory cell MCELL. The reference stage RFST is passed through by the current Iref by the current mirror effect between the transistors TP1 and TP0, and the drain of the transistor TP2 of the read stage RDST also delivers the current Iref by the current mirror effect with the transistor TP0. If the current Icell is higher than Iref, the voltage VMAT drops, the transistor TP3 goes into a transmission state and the output DATAOUT goes to 1. If the current Icell is lower than Iref, the voltage VKAT stays at the high level and the output DATAOUT stays at 0.
As indicated above, other types of read amplifiers comprise an output stage with an inverting gate. In this case, the differential stage DIFST1 is replaced by an inverting gate that receives the signal VMAT at input and the output of which forms the output DATAOUT of the read amplifier. In this case, the output DATAOUT is at 1 or at 0 depending on whether the signal VMAT is lower or higher than a trip point of the inverting gate.
The advantage of a read amplifier with a differential output stage of the type that has just been described is that it is accurate because the value of the output DATAOUT does not depend on the trip point of an inverting gate, and is a function of a comparison of the voltage VMAT with the reference voltage Vref. Therefore, the output DATAOUT goes to 0 as soon as VMAT becomes lower than Vref.
Another advantage of such a read amplifier is that it has a short read time as the voltage Vref is generally higher than the trip point of an inverting gate, such that the detection of the low level of the voltage VMAT is faster with a differential stage than with an inverting gate. However, such a read amplifier has a double drawback. First, the differential output stage is more complex than an output stage with an inverting gate (two MOS transistors being sufficient to obtain an inverting gate). Furthermore, the electrical consumption of the differential output stage is considerable while the electrical consumption of an inverting gate is zero outside commutation periods.
An object of the present invention is to provide a read amplifier of the type described above in which the differential stage is of a simpler structure and has a lower current consumption.
This object is achieved by providing a read amplifier comprising a read stage linked or intended to be linked to a memory cell that is to be read, a reference stage that is passed through by a reference current, and a differential output stage comprising PMOS and NMOS type transistors. The transistors of the differential stage may comprise only one PMOS transistor and one NMOS transistor in series. The PMOS transistor may have its gate linked to one node of the read stage. The NMOS transistor may have its gate linked to the gate of a transistor of the reference stage on which a gate voltage occurs that is representative of the reference current. The mid-point of the PMOS and NMOS transistors may form a data output node of the read amplifier.
According to one embodiment, the read stage may comprise a PMOS transistor receiving a reference voltage at its gate, in series with an NMOS transistor the source of which forms a link point of the read amplifier to a memory cell. The drain of the PMOS transistor of the read stage may be linked to the gate of the PMOS transistor of the differential stage.
According to another embodiment, the reference stage may comprise a PMOS transistor receiving the reference voltage at its gate, in series with an NMOS transistor having its gate linked to the gate of the NMOS transistor of the differential stage.
According to one embodiment, the gate of the NMOS transistor of the read stage may be linked to the drain of the NMOS transistor of the reference stage. The gate of the NMOS transistor of the reference stage may be linked to the source of the NMOS transistor of the read stage.
According to another embodiment, the read amplifier may comprise a precharge transistor linked to the drain of the NMOS transistor of the read stage. The precharge transistor may have its gate driven by the data output node of the read amplifier.
The present invention also relates to a non-volatile memory comprising a memory array having at least one memory cell, and at least one read amplifier as defined above. The memory cell may comprise a floating-gate transistor.